An input stage circuit is a basic building block for analog or mixed signal circuits. A first stage of an analog or mixed signal circuit may typically include an input stage circuit operating over a rail-to-rail (“rail-to-rail”) input common mode voltage range. A rail-to-rail input stage circuit is designed to handle a wide input common mode voltage range. Typically the rail-to-rail input stage circuit is designed to handle an input common mode voltage ranging from negative supply voltage rail (or ground) all the way up to the positive supply voltage rail, hence the name rail-to-rail. Examples of such analog or mixed signal circuits include operational amplifiers, comparators, and analog-to-digital converters.
Analog or mixed signal circuits used in low-voltage integrated circuit manufacturing processes normally require a differential input stage circuit that can operate when the input common mode voltage approaches the supply rails. Conventional rail-to-rail input stage circuits use two complimentary differential transistor pair circuits including a first differential pair circuit (“N_diff_pair”) comprising a pair of matched N-type metal-oxide semiconductor (“NMOS”) transistors and a second differential pair circuit (“P_diff_pair”) comprising a pair of matched P-type metal-oxide-semiconductor (“PMOS”) transistors. FIG. 1 depicts a typical N differential pair circuit and FIG. 2 depicts a typical P differential pair circuit according to the prior art.
The input common mode of differential pairs is limited. For the N_diff_pair, the input common mode is limited to the voltage range from VSS+Vth+2*VDsat to VDD, where VDD is the positive supply voltage, VSS is the negative supply voltage (ground), Vth is the threshold voltage of metal-oxide-semiconductor (“MOS”) transistors M1 and M2, and VDsat is the saturation voltage for MOS transistors M0, M1, and M2. For the P_diff_pair, the input common mode is limited to the voltage range from VSS to VDD−Vth−2*VDsat. Thus, when VDD>VSS+2*(Vth+2VDsat), the combination of P_diff_pair and N_diff_pair can be used to support the entire common mode range from the negative supply voltage to the positive supply voltage.
FIG. 3 is an example of a rail-to-rail input stage circuit including complementary differential pairs of transistors according to the prior art. Rail-to-rail input stage circuit 30 includes first stage circuit 300 and second stage circuit 330. The first stage circuit 300 includes a first differential pair 310 and a second differential pair 320, where the first differential pair 310 is a P_diff_pair and the second differential pair 320 is an N_diff_pair, similar to the P_diff_pair and the N_diff_pair described FIGS. 1 and 2.
The rail-to-rail input stage circuit 30 shown in FIG. 3 is also known as a two-stage “folded cascode” amplifier since the second stage circuit 330 combines (folds) the current flowing through P_diff_pair 310 with the current flowing through the N_diff_pair 320. Because these currents inherently flow in opposite directions, the second stage circuit 330 is necessary to fold and sum the currents flowing through P_diff_pair 310 and N_diff_pair 320.
A drawback of rail-to-rail input stage circuit 30, which uses complementary differential pairs, is the requirement of a second stage circuit. The second stage circuit limits the bandwidth and operational speed of the rail-to-rail input stage circuit, and also requires additional die area. As a result, the bandwidth and speed of any circuit embodying this type of rail-to-rail input stage will also be limited. In addition, since both NMOS and PMOS devices are used, this solution is more sensitive to variations in the manufacturing process. Further it is a design challenge to optimize the design of rail-to-rail input stage circuit 30 to account for noise, power consumption, and/or speed.
More recently, rail-to-rail input stage circuits have been developed based on non-complementary differential pairs, which include two sets of the same type of differential pairs (NMOS or PMOS) to overcome the shortcomings of the rail-to-rail input stage circuits that use complementary differential pairs. One proposed solution using rail-to-rail input stage circuits based on non-complementary differential pairs is described in U.S. Pat. No. 8,102,211 to Shi (“Shi Patent”). The Shi Patent utilizes a dynamic bias control circuit that controls the bias current through the second differential pair circuit to maintain the output impedance of the rail-to-rail input stage circuit.
FIG. 4 depicts an example rail-to-rail input stage circuit utilizing non-complementary differential pairs with a dynamic bias control circuit according to the prior art. It provides a differential pair circuit 410 coupled with a level-shifted differential pair circuit 440, and a bias control circuit 430. The differential pair circuit 410 and the level-shifted differential pair 440 include the same type of MOS devices, also known as non-complementary MOS devices. These MOS devices can be either NMOS or PMOS devices.
The bias control circuit 430 monitors the input common mode voltage (“Vicm”) of the rail-to-rail input stage circuit and gradually reduces the bias current through the level-shifted differential pair 440; and eventually cuts it down to zero. The bias control circuit 430 includes MOS transistors M3L and Mnb. MOS transistor M3L functions as a voltage sensor that detects the input common mode voltage Vicm of the rail-to-rail input stage circuit 40, and the MOS transistor Mnb functions as a current mirror that mirrors a tracking current “Ib” inversely proportional to Vicm to the current source M0b of the level-shifted differential pair circuit 440. The current source Mpb provides the necessary bias current to the bias control circuit 430. The voltage sensor M3L is controlled by the input common mode voltage Vicm. When Vicm is higher than VDD−Vth−VDsat, the voltage sensor M3L detects this condition and generates a tracking current inversely proportional to the Vicm.
The differential pair circuit 410 includes a differential transistor pair of matched NMOS transistors M1a and M2a coupled with a current source transistor M0a. The level-shifted differential pair circuit 440 comprises a source follower circuit 442 coupled with a differential pair circuit 420. The source follower circuit 442 includes a pair of matched PMOS transistors M1L and M2L coupled with two bias current sources 448 and 450, respectively. The differential pair circuit 420 includes a differential transistor pair of matched NMOS transistors M1b and M2b and the current source transistor M0b discussed above.
In operation, the source follower circuit 442 shifts up the voltage level of the input signal at the input of the rail-to-rail input stage circuit 40. As a result, when Vicm is outside the input common mode voltage range supported by the level-shifted differential pair circuit 440, the level-shifted differential circuit 440 does not affect the normal operation of differential pair circuit 410, and, therefore, the operation of the rail-to-rail input stage circuit 40. Bias control circuit 430 does not allow MOS transistors M1b and M2b to enter into the ohmic (linear) region, and thus does not allow reduction of the overall output impedance, and consequently the gain, of rail-to-rail input stage circuit 40.
The bias control scheme of the Shi Patent, however, is based on the assumption that VDD=2*(Vth+VDSAT). When VDD is much higher, both of the differential pairs 410 and 420 conduct current. As a result, the transconductance (“gm”) is therefore not constant over the range of input common mode voltages. It is desirable to maintain constant transconductance over the range of input common mode voltages because constant transconductance makes frequency compensation much easier and more robust when a rail-to-rail input stage is used in a feedback network. Constant transconductance can also reduce the harmonic and variation in the circuit speed. Additionally the circuit technique disclosed in the Shi Patent cannot achieve constant gm without adding several levels of additional complex logic.